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CLC number: TN402
On-line Access: 2024-05-06
Received: 2023-07-05
Revision Accepted: 2024-05-06
Crosschecked: 2023-12-17
Cited: 0
Clicked: 203
Citations: Bibtex RefMan EndNote GB/T7714
Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
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Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU. Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH[J]. Frontiers of Information Technology & Electronic Engineering, 2024, 25(4): 485-499.
@article{title="Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH",
author="Zhengzhou CAO, Guozhu LIU, Yanfei ZHANG, Yueer SHAN, Yuting XU",
journal="Frontiers of Information Technology & Electronic Engineering",
volume="25",
number="4",
pages="485-499",
year="2024",
publisher="Zhejiang University Press & Springer",
doi="10.1631/FITEE.2300454"
}
%0 Journal Article
%T Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
%A Zhengzhou CAO
%A Guozhu LIU
%A Yanfei ZHANG
%A Yueer SHAN
%A Yuting XU
%J Frontiers of Information Technology & Electronic Engineering
%V 25
%N 4
%P 485-499
%@ 2095-9184
%D 2024
%I Zhejiang University Press & Springer
%DOI 10.1631/FITEE.2300454
TY - JOUR
T1 - Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH
A1 - Zhengzhou CAO
A1 - Guozhu LIU
A1 - Yanfei ZHANG
A1 - Yueer SHAN
A1 - Yuting XU
J0 - Frontiers of Information Technology & Electronic Engineering
VL - 25
IS - 4
SP - 485
EP - 499
%@ 2095-9184
Y1 - 2024
PB - Zhejiang University Press & Springer
ER -
DOI - 10.1631/FITEE.2300454
Abstract: This paper proposes a kind of programmable logic element (PLE) based on sense-Switch pFLASH technology. By programming sense-Switch pFLASH, all three-bit look-up table (LUT3) functions, partial four-bit look-up table (LUT4) functions, latch functions, and d flip flop (DFF) with enable and reset functions can be realized. Because PLE uses a choice of operational logic (COOL) approach for the operation of logic functions, it allows any logic circuit to be implemented at any ratio of combinatorial logic to register. This intrinsic property makes it close to the basic application specific integrated circuit (ASIC) cell in terms of fine granularity, thus allowing ASIC-like cell-based mappers to apply all their optimization potential. By measuring sense-Switch pFLASH and PLE circuits, the results show that the “on” state driving current of the sense-Switch pFLASH is about 245.52 μA, and that the “off” state leakage current is about 0.1 pA. The programmable function of PLE works normally. The delay of the typical combinatorial logic operation AND3 is 0.69 ns, and the delay of the sequential logic operation DFF is 0.65 ns, both of which meet the requirements of the design technical index.
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